/*
    Copyright (C) 2011  Jiabo <jiabo2011@gmail.com>

    This program is free software; you can redistribute it and/or modify
    it under the terms of the GNU General Public License as published by
    the Free Software Foundation; either version 2 of the License, or
    (at your option) any later version.

    This program is distributed in the hope that it will be useful,
    but WITHOUT ANY WARRANTY; without even the implied warranty of
    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
    GNU General Public License for more details.

    You should have received a copy of the GNU General Public License
    along with this program; if not, write to the Free Software
    Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
*/

/*
	r4 points to IA-32 register context block
	r5 points to IA-32 memory image
	r6 contains IA-32 ISA PC value
*/

#ifndef __ASSEMBLY__

#define arm_r0		0
#define arm_r1		1
#define arm_r2		2
#define arm_r3		3
#define arm_r4		4
#define arm_r5		5
#define arm_r6		6
#define arm_r7		7
#define arm_r8		8
#define arm_r9		9
#define arm_r10		10
#define arm_r11		11
#define arm_r12		12
#define arm_sp		13
#define arm_lr		14
#define arm_pc		15

#else

#define arm_r0		r0
#define arm_r1		r1
#define arm_r2		r2
#define arm_r3		r3
#define arm_r4		r4
#define arm_r5		r5
#define arm_r6		r6
#define arm_r7		r7
#define arm_r8		r8
#define arm_r9		r9
#define arm_r10		sl
#define arm_r11		fp
#define arm_r12		ip
#define arm_sp		sp
#define arm_lr		lr
#define arm_pc		pc

#endif

#define T0		arm_r0
#define T1		arm_r1
#define T2		arm_r2
#define R0		arm_r3
#define CB		arm_r4
#define MI		arm_r5
#define SPC		arm_r6
#define OPC		arm_r7
#define OP1		arm_r8
#define OP2		arm_r9

